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Révision	c8dad001bb20c4775c8465477538226e5471e3c0 (tree)
l'heure	2015-12-10 02:39:39
Auteur	Yoshinori Sato <ysato@sa76...>
Commiter	Yoshinori Sato

Message de Log

RXv2 instructions support.

Change Summary

modified: gcc/config/rx/constraints.md (diff)
modified: gcc/config/rx/rx-opts.h (diff)
modified: gcc/config/rx/rx.c (diff)
modified: gcc/config/rx/rx.h (diff)
modified: gcc/config/rx/rx.md (diff)
modified: gcc/config/rx/rx.opt (diff)
add: gcc/config/rx/sync.md (diff)
modified: gcc/config/rx/t-rx (diff)
modified: gcc/doc/md.texi (diff)

Modification

--- a/gcc/config/rx/constraints.md

+++ b/gcc/config/rx/constraints.md

		@@ -106,3 +106,10 @@
106	106	)
107	107	)
108	108	)
	109	+
	110	+(define_memory_constraint "q"
	111	+ "A MEM which only uses REG addressing."
	112	+ (and (match_code "mem")
	113	+ (match_code "reg" "0")
	114	+ )
	115	+)

--- a/gcc/config/rx/rx-opts.h

+++ b/gcc/config/rx/rx-opts.h

		@@ -25,7 +25,8 @@ enum rx_cpu_types
25	25	RX600,
26	26	RX610,
27	27	RX200,
28		- RX100
	28	+ RX100,
	29	+ RXV2
29	30	};
30	31
31	32	#endif

--- a/gcc/config/rx/rx.c

+++ b/gcc/config/rx/rx.c

		@@ -639,6 +639,19 @@ rx_print_operand (FILE * file, rtx op, int letter)
639	639	case 0xa: fprintf (file, "isp"); break;
640	640	case 0xb: fprintf (file, "fintv"); break;
641	641	case 0xc: fprintf (file, "intb"); break;
	642	+ case 0xd:
	643	+ if (ALLOW_RXV2_INSNS)
	644	+ {
	645	+ fprintf (file, "extb"); break;
	646	+ }
	647	+ goto invalid_register;
	648	+ case 0x40:
	649	+ case 0x41:
	650	+ if (ALLOW_RXV2_INSNS)
	651	+ {
	652	+ fprintf (file, "a%ld", INTVAL(op) - 0x40); break;
	653	+ } /* RXv1 fall through */
	654	+ invalid_register:
642	655	default:
643	656	warning (0, "unrecognized control register number: %d - using 'psw'",
644	657	(int) INTVAL (op));

		@@ -731,6 +744,11 @@ rx_print_operand (FILE * file, rtx op, int letter)
731	744	fprintf (file, "%s", reg_names [rx_pid_base_regnum ()]);
732	745	break;
733	746
	747	+ case 'V':
	748	+ gcc_assert (CONST_INT_P (op));
	749	+ fprintf (file, "a%ld", INTVAL(op));
	750	+ break;
	751	+
734	752	case 'R':
735	753	gcc_assert (GET_MODE_SIZE (GET_MODE (op)) <= 4);
736	754	unsigned_load = true;

		@@ -1772,12 +1790,32 @@ rx_expand_prologue (void)
1772	1790	/* We have assumed that there are at least two registers pushed... */
1773	1791	gcc_assert (acc_high != 0);
1774	1792
1775		- /* Note - the bottom 16 bits of the accumulator are inaccessible.
1776		- We just assume that they are zero. */
1777		- emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1778		- emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1779		- emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
1780		- emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
	1793	+ if (!ALLOW_RXV2_INSNS)
	1794	+ {
	1795	+ /* Note - the bottom 16 bits of the accumulator are inaccessible.
	1796	+ We just assume that they are zero. */
	1797	+ emit_insn ( gen_mvfacmi (
	1798	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(64)));
	1799	+ emit_insn (gen_mvfachi (
	1800	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(64)));
	1801	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
	1802	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
	1803	+ }
	1804	+ else
	1805	+ {
	1806	+ emit_insn ( gen_mvfaclo (
	1807	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(64)));
	1808	+ emit_insn (gen_mvfachi (
	1809	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(64)));
	1810	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
	1811	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
	1812	+ emit_insn ( gen_mvfaclo (
	1813	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(65)));
	1814	+ emit_insn (gen_mvfachi (
	1815	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(65)));
	1816	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
	1817	+ emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
	1818	+ }
1781	1819	}
1782	1820	else
1783	1821	{

		@@ -1787,10 +1825,30 @@ rx_expand_prologue (void)
1787	1825	/* We have assumed that there are at least two registers pushed... */
1788	1826	gcc_assert (acc_high <= high);
1789	1827
1790		- emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1791		- emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1792		- emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
1793		- gen_rx_store_vector (acc_low, acc_high)));
	1828	+ if (!ALLOW_RXV2_INSNS)
	1829	+ {
	1830	+ emit_insn (gen_mvfacmi (
	1831	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(64)));
	1832	+ emit_insn (gen_mvfachi (
	1833	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(64)));
	1834	+ emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
	1835	+ gen_rx_store_vector (acc_low, acc_high)));
	1836	+ }
	1837	+ else
	1838	+ {
	1839	+ emit_insn (gen_mvfacmi (
	1840	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(64)));
	1841	+ emit_insn (gen_mvfachi (
	1842	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(64)));
	1843	+ emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
	1844	+ gen_rx_store_vector (acc_low, acc_high)));
	1845	+ emit_insn (gen_mvfacmi (
	1846	+ gen_rtx_REG (SImode, acc_low), GEN_INT(0), GEN_INT(65)));
	1847	+ emit_insn (gen_mvfachi (
	1848	+ gen_rtx_REG (SImode, acc_high), GEN_INT(0), GEN_INT(65)));
	1849	+ emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
	1850	+ gen_rx_store_vector (acc_low, acc_high)));
	1851	+ }
1794	1852	}
1795	1853	}
1796	1854

		@@ -2100,41 +2158,83 @@ rx_expand_epilogue (bool is_sibcall)
2100	2158	if (MUST_SAVE_ACC_REGISTER)
2101	2159	{
2102	2160	unsigned int acc_low, acc_high;
2103		-
2104		- /* Reverse the saving of the accumulator register onto the stack.
2105		- Note we must adjust the saved "low" accumulator value as it
2106		- is really the middle 32-bits of the accumulator. */
2107		- if (register_mask)
	2161	+ if (!ALLOW_RXV2_INSNS)
2108	2162	{
2109		- acc_low = acc_high = 0;
	2163	+ /* Reverse the saving of the accumulator register onto the stack.
	2164	+ Note we must adjust the saved "low" accumulator value as it
	2165	+ is really the middle 32-bits of the accumulator. */
	2166	+ if (register_mask)
	2167	+ {
	2168	+ acc_low = acc_high = 0;
2110	2169
2111		- for (reg = 1; reg < CC_REGNUM; reg ++)
2112		- if (register_mask & (1 << reg))
2113		- {
2114		- if (acc_low == 0)
2115		- acc_low = reg;
2116		- else
	2170	+ for (reg = 1; reg < CC_REGNUM; reg ++)
	2171	+ if (register_mask & (1 << reg))
2117	2172	{
2118		- acc_high = reg;
2119		- break;
	2173	+ if (acc_low == 0)
	2174	+ acc_low = reg;
	2175	+ else
	2176	+ {
	2177	+ acc_high = reg;
	2178	+ break;
	2179	+ }
2120	2180	}
2121		- }
2122		- emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
2123		- emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
	2181	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
	2182	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
	2183	+ }
	2184	+ else
	2185	+ {
	2186	+ acc_low = low;
	2187	+ acc_high = low + 1;
	2188	+ emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
	2189	+ gen_rx_popm_vector (acc_low, acc_high)));
	2190	+ }
	2191	+
	2192	+ emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode, acc_low),
	2193	+ gen_rtx_REG (SImode, acc_low),
	2194	+ GEN_INT (16)));
	2195	+ emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low), GEN_INT(0)));
	2196	+ emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high), GEN_INT(0)));
2124	2197	}
2125	2198	else
2126	2199	{
2127		- acc_low = low;
2128		- acc_high = low + 1;
2129		- emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
2130		- gen_rx_popm_vector (acc_low, acc_high)));
2131		- }
	2200	+ if (register_mask)
	2201	+ {
	2202	+ acc_low = acc_high = 0;
2132	2203
2133		- emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode, acc_low),
2134		- gen_rtx_REG (SImode, acc_low),
2135		- GEN_INT (16)));
2136		- emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low)));
2137		- emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high)));
	2204	+ for (reg = 1; reg < CC_REGNUM; reg ++)
	2205	+ if (register_mask & (1 << reg))
	2206	+ {
	2207	+ if (acc_low == 0)
	2208	+ acc_low = reg;
	2209	+ else
	2210	+ {
	2211	+ acc_high = reg;
	2212	+ break;
	2213	+ }
	2214	+ }
	2215	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
	2216	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
	2217	+ emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low), GEN_INT(0)));
	2218	+ emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high), GEN_INT(0)));
	2219	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
	2220	+ emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
	2221	+ emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low), GEN_INT(1)));
	2222	+ emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high), GEN_INT(1)));
	2223	+ }
	2224	+ else
	2225	+ {
	2226	+ acc_low = low;
	2227	+ acc_high = low + 1;
	2228	+ emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
	2229	+ gen_rx_popm_vector (acc_low, acc_high)));
	2230	+ emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low), GEN_INT(0)));
	2231	+ emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high), GEN_INT(0)));
	2232	+ emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
	2233	+ gen_rx_popm_vector (acc_low, acc_high)));
	2234	+ emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low), GEN_INT(1)));
	2235	+ emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high), GEN_INT(1)));
	2236	+ }
	2237	+ }
2138	2238	}
2139	2239
2140	2240	if (register_mask)

		@@ -2350,6 +2450,28 @@ enum rx_builtin
2350	2450	RX_BUILTIN_ROUND,
2351	2451	RX_BUILTIN_SETPSW,
2352	2452	RX_BUILTIN_WAIT,
	2453	+ RX_BUILTIN_MACHI2,
	2454	+ RX_BUILTIN_MACLO2,
	2455	+ RX_BUILTIN_MULHI2,
	2456	+ RX_BUILTIN_MULLO2,
	2457	+ RX_BUILTIN_MVFACHI2,
	2458	+ RX_BUILTIN_MVFACMI2,
	2459	+ RX_BUILTIN_MVTACHI2,
	2460	+ RX_BUILTIN_MVTACLO2,
	2461	+ RX_BUILTIN_RACW2,
	2462	+ RX_BUILTIN_EMACA,
	2463	+ RX_BUILTIN_EMSBA,
	2464	+ RX_BUILTIN_EMULA,
	2465	+ RX_BUILTIN_MACLH,
	2466	+ RX_BUILTIN_MSBHI,
	2467	+ RX_BUILTIN_MSBLO,
	2468	+ RX_BUILTIN_MSBLH,
	2469	+ RX_BUILTIN_MVFACGU,
	2470	+ RX_BUILTIN_MVFACLO,
	2471	+ RX_BUILTIN_MVTACGU,
	2472	+ RX_BUILTIN_RACL,
	2473	+ RX_BUILTIN_RDACL,
	2474	+ RX_BUILTIN_RDACW,
2353	2475	RX_BUILTIN_max
2354	2476	};
2355	2477

		@@ -2416,6 +2538,26 @@ rx_init_builtins (void)
2416	2538	ADD_RX_BUILTIN1 (ROUND, "round", intSI, float);
2417	2539	ADD_RX_BUILTIN1 (REVW, "revw", intSI, intSI);
2418	2540	ADD_RX_BUILTIN0 (WAIT, "wait", void);
	2541	+ ADD_RX_BUILTIN3 (MACHI2, "machi2", void, intSI, intSI, integer);
	2542	+ ADD_RX_BUILTIN3 (MACLO2, "maclo2", void, intSI, intSI, integer);
	2543	+ ADD_RX_BUILTIN3 (MULHI2, "mulhi2", void, intSI, intSI, integer);
	2544	+ ADD_RX_BUILTIN3 (MULLO2, "mullo2", void, intSI, intSI, integer);
	2545	+ ADD_RX_BUILTIN2 (MVFACHI2,"mvfachi2",intSI, integer, integer);
	2546	+ ADD_RX_BUILTIN2 (MVFACMI2,"mvfacmi2",intSI, integer, integer);
	2547	+ ADD_RX_BUILTIN2 (MVTACHI2,"mvtachi2",void, intSI, integer);
	2548	+ ADD_RX_BUILTIN2 (MVTACLO2,"mvtaclo2",void, intSI, integer);
	2549	+ ADD_RX_BUILTIN3 (EMACA, "emaca", void, intSI, intSI, integer);
	2550	+ ADD_RX_BUILTIN3 (EMSBA, "emsba", void, intSI, intSI, integer);
	2551	+ ADD_RX_BUILTIN3 (MACLH, "maclh", void, intSI, intSI, integer);
	2552	+ ADD_RX_BUILTIN3 (MSBHI, "msbhi", void, intSI, intSI, integer);
	2553	+ ADD_RX_BUILTIN3 (MSBLO, "msblo", void, intSI, intSI, integer);
	2554	+ ADD_RX_BUILTIN3 (MSBLH, "msblh", void, intSI, intSI, integer);
	2555	+ ADD_RX_BUILTIN2 (MVFACGU, "mvfacgu", intSI, intSI, integer);
	2556	+ ADD_RX_BUILTIN2 (MVFACLO, "mvfaclo", intSI, intSI, integer);
	2557	+ ADD_RX_BUILTIN2 (MVTACGU, "mvtacgu", void, intSI, integer);
	2558	+ ADD_RX_BUILTIN2 (RACL, "racl", void, intSI, integer);
	2559	+ ADD_RX_BUILTIN2 (RDACL, "rdacl", void, intSI, integer);
	2560	+ ADD_RX_BUILTIN2 (RDACW, "rdacw", void, intSI, integer);
2419	2561	}
2420	2562
2421	2563	/* Return the RX builtin for CODE. */

		@@ -2492,7 +2634,7 @@ rx_expand_builtin_mvtipl (rtx arg)
2492	2634	}
2493	2635
2494	2636	static rtx
2495		-rx_expand_builtin_mac (tree exp, rtx (* gen_func)(rtx, rtx))
	2637	+rx_expand_builtin_mac (tree exp, rtx (* gen_func)(rtx, rtx, rtx))
2496	2638	{
2497	2639	rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
2498	2640	rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));

		@@ -2503,36 +2645,172 @@ rx_expand_builtin_mac (tree exp, rtx (* gen_func)(rtx, rtx))
2503	2645	if (! REG_P (arg2))
2504	2646	arg2 = force_reg (SImode, arg2);
2505	2647
2506		- emit_insn (gen_func (arg1, arg2));
	2648	+ emit_insn (gen_func (arg1, arg2, GEN_INT(64)));
2507	2649
2508	2650	return NULL_RTX;
2509	2651	}
2510	2652
2511	2653	static rtx
2512		-rx_expand_int_builtin_1_arg (rtx arg,
2513		- rtx target,
2514		- rtx (* gen_func)(rtx, rtx),
2515		- bool mem_ok)
	2654	+rx_expand_builtin_mac2 (tree exp, rtx (* gen_func)(rtx, rtx, rtx))
2516	2655	{
2517		- if (! REG_P (arg))
2518		- if (!mem_ok \|\| ! MEM_P (arg))
2519		- arg = force_reg (SImode, arg);
	2656	+ rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
	2657	+ rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
	2658	+ rtx arg3 = expand_normal (CALL_EXPR_ARG (exp, 2));
	2659	+ int acc;
	2660	+
	2661	+ if (!ALLOW_RXV2_INSNS)
	2662	+ {
	2663	+ error("Required RXv2 instructions.");
	2664	+ return NULL_RTX;
	2665	+ }
	2666	+
	2667	+ if (! REG_P (arg1))
	2668	+ arg1 = force_reg (SImode, arg1);
	2669	+
	2670	+ if (! REG_P (arg2))
	2671	+ arg2 = force_reg (SImode, arg2);
2520	2672
	2673	+ if (! CONST_INT_P (arg3))
	2674	+ return NULL_RTX;
	2675	+
	2676	+ acc = INTVAL(arg3);
	2677	+ if (acc < 0 \|\| acc > 1)
	2678	+ {
	2679	+ error("Invalid register number.");
	2680	+ return NULL_RTX;
	2681	+ }
	2682	+
	2683	+ emit_insn (gen_func (arg1, arg2, GEN_INT(acc + 64)));
	2684	+
	2685	+ return NULL_RTX;
	2686	+}
	2687	+
	2688	+static rtx
	2689	+rx_expand_builtin_fromacc (rtx target, rtx (* gen_func)(rtx, rtx, rtx))
	2690	+{
2521	2691	if (target == NULL_RTX \|\| ! REG_P (target))
2522	2692	target = gen_reg_rtx (SImode);
2523	2693
2524		- emit_insn (gen_func (target, arg));
	2694	+ emit_insn (gen_func (target, GEN_INT(0), GEN_INT(64)));
	2695	+
	2696	+ return target;
	2697	+}
	2698	+
	2699	+static rtx
	2700	+rx_expand_builtin_fromacc2 (rtx target, tree exp, rtx (* gen_func)(rtx, rtx, rtx))
	2701	+{
	2702	+ rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
	2703	+ rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
	2704	+ int acc;
	2705	+
	2706	+ if (!ALLOW_RXV2_INSNS)
	2707	+ {
	2708	+ error("Required RXv2 instructions.");
	2709	+ return NULL_RTX;
	2710	+ }
	2711	+
	2712	+ if (target == NULL_RTX \|\| ! REG_P (target))
	2713	+ target = gen_reg_rtx (SImode);
	2714	+
	2715	+ if (! CONST_INT_P (arg1) \|\| ! CONST_INT_P (arg2))
	2716	+ return NULL_RTX;
	2717	+
	2718	+ acc = INTVAL(arg2);
	2719	+ if (acc < 0 \|\| acc > 1)
	2720	+ {
	2721	+ error("Invalid accumlator number.");
	2722	+ return NULL_RTX;
	2723	+ }
	2724	+
	2725	+ if (INTVAL(arg1) < 0 \|\| INTVAL(arg1) > 2)
	2726	+ {
	2727	+ error("Invalid shift count.");
	2728	+ return NULL_RTX;
	2729	+ }
	2730	+
	2731	+ emit_insn (gen_func (target, arg1, GEN_INT(acc+64)));
2525	2732
2526	2733	return target;
2527	2734	}
2528	2735
2529	2736	static rtx
2530		-rx_expand_int_builtin_0_arg (rtx target, rtx (* gen_func)(rtx))
	2737	+rx_expand_builtin_toacc (rtx arg, rtx (* gen_func)(rtx, rtx))
2531	2738	{
	2739	+ if (! REG_P (arg))
	2740	+ arg = force_reg (SImode, arg);
	2741	+
	2742	+ emit_insn (gen_func (arg, GEN_INT(64)));
	2743	+
	2744	+ return NULL_RTX;
	2745	+}
	2746	+
	2747	+static rtx
	2748	+rx_expand_builtin_toacc2 (tree exp, rtx (* gen_func)(rtx, rtx))
	2749	+{
	2750	+ rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
	2751	+ rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
	2752	+ int acc;
	2753	+
	2754	+ if (!ALLOW_RXV2_INSNS)
	2755	+ {
	2756	+ error("Required RXv2 instructions.");
	2757	+ return NULL_RTX;
	2758	+ }
	2759	+
	2760	+ if (! REG_P (arg1))
	2761	+ arg1 = force_reg (SImode, arg1);
	2762	+
	2763	+ acc = INTVAL(arg2);
	2764	+ if (acc < 0 \|\| acc > 1)
	2765	+ {
	2766	+ error("Invalid accumlator number.");
	2767	+ return NULL_RTX;
	2768	+ }
	2769	+
	2770	+ emit_insn (gen_func (arg1, GEN_INT(acc + 64)));
	2771	+
	2772	+ return NULL_RTX;
	2773	+}
	2774	+
	2775	+static rtx
	2776	+rx_expand_builtin_rac (tree exp, rtx (* gen_func)(rtx, rtx))
	2777	+{
	2778	+ rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
	2779	+ rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
	2780	+ int acc;
	2781	+
	2782	+ if (!ALLOW_RXV2_INSNS)
	2783	+ {
	2784	+ error("Required RXv2 instructions.");
	2785	+ return NULL_RTX;
	2786	+ }
	2787	+
	2788	+ acc = INTVAL(arg2);
	2789	+ if (acc < 0 \|\| acc > 1)
	2790	+ {
	2791	+ error("Invalid accumlator number.");
	2792	+ return NULL_RTX;
	2793	+ }
	2794	+
	2795	+ emit_insn (gen_func (arg1, GEN_INT(acc + 64)));
	2796	+
	2797	+ return NULL_RTX;
	2798	+}
	2799	+
	2800	+static rtx
	2801	+rx_expand_int_builtin_1_arg (rtx arg,
	2802	+ rtx target,
	2803	+ rtx (* gen_func)(rtx, rtx),
	2804	+ bool mem_ok)
	2805	+{
	2806	+ if (! REG_P (arg))
	2807	+ if (!mem_ok \|\| ! MEM_P (arg))
	2808	+ arg = force_reg (SImode, arg);
	2809	+
2532	2810	if (target == NULL_RTX \|\| ! REG_P (target))
2533	2811	target = gen_reg_rtx (SImode);
2534	2812
2535		- emit_insn (gen_func (target));
	2813	+ emit_insn (gen_func (target, arg));
2536	2814
2537	2815	return target;
2538	2816	}

		@@ -2606,14 +2884,14 @@ rx_expand_builtin (tree exp,
2606	2884	case RX_BUILTIN_MACLO: return rx_expand_builtin_mac (exp, gen_maclo);
2607	2885	case RX_BUILTIN_MULHI: return rx_expand_builtin_mac (exp, gen_mulhi);
2608	2886	case RX_BUILTIN_MULLO: return rx_expand_builtin_mac (exp, gen_mullo);
2609		- case RX_BUILTIN_MVFACHI: return rx_expand_int_builtin_0_arg
	2887	+ case RX_BUILTIN_MVFACHI: return rx_expand_builtin_fromacc
2610	2888	(target, gen_mvfachi);
2611		- case RX_BUILTIN_MVFACMI: return rx_expand_int_builtin_0_arg
	2889	+ case RX_BUILTIN_MVFACMI: return rx_expand_builtin_fromacc
2612	2890	(target, gen_mvfacmi);
2613		- case RX_BUILTIN_MVTACHI: return rx_expand_void_builtin_1_arg
2614		- (op, gen_mvtachi, true);
2615		- case RX_BUILTIN_MVTACLO: return rx_expand_void_builtin_1_arg
2616		- (op, gen_mvtaclo, true);
	2891	+ case RX_BUILTIN_MVTACHI: return rx_expand_builtin_toacc
	2892	+ (op, gen_mvtachi);
	2893	+ case RX_BUILTIN_MVTACLO: return rx_expand_builtin_toacc
	2894	+ (op, gen_mvtaclo);
2617	2895	case RX_BUILTIN_RMPA:
2618	2896	if (rx_allow_string_insns)
2619	2897	emit_insn (gen_rmpa ());

		@@ -2623,13 +2901,44 @@ rx_expand_builtin (tree exp,
2623	2901	case RX_BUILTIN_MVFC: return rx_expand_builtin_mvfc (arg, target);
2624	2902	case RX_BUILTIN_MVTC: return rx_expand_builtin_mvtc (exp);
2625	2903	case RX_BUILTIN_MVTIPL: return rx_expand_builtin_mvtipl (op);
2626		- case RX_BUILTIN_RACW: return rx_expand_void_builtin_1_arg
2627		- (op, gen_racw, false);
	2904	+ case RX_BUILTIN_RACW:
	2905	+ emit_insn (gen_racw (op, GEN_INT(64))); return NULL_RTX;
2628	2906	case RX_BUILTIN_ROUND: return rx_expand_builtin_round (op, target);
2629	2907	case RX_BUILTIN_REVW: return rx_expand_int_builtin_1_arg
2630	2908	(op, target, gen_revw, false);
2631	2909	case RX_BUILTIN_WAIT: emit_insn (gen_wait ()); return NULL_RTX;
2632		-
	2910	+ case RX_BUILTIN_MACHI2: return rx_expand_builtin_mac2 (exp, gen_machi);
	2911	+ case RX_BUILTIN_MACLO2: return rx_expand_builtin_mac2 (exp, gen_maclo);
	2912	+ case RX_BUILTIN_MULHI2: return rx_expand_builtin_mac2 (exp, gen_mulhi);
	2913	+ case RX_BUILTIN_MULLO2: return rx_expand_builtin_mac2 (exp, gen_mullo);
	2914	+ case RX_BUILTIN_MVFACHI2: return rx_expand_builtin_fromacc2
	2915	+ (target, exp, gen_mvfachi);
	2916	+ case RX_BUILTIN_MVFACMI2: return rx_expand_builtin_fromacc2
	2917	+ (target, exp, gen_mvfacmi);
	2918	+ case RX_BUILTIN_MVTACHI2: return rx_expand_builtin_toacc2
	2919	+ (exp, gen_mvtachi);
	2920	+ case RX_BUILTIN_MVTACLO2: return rx_expand_builtin_toacc2
	2921	+ (exp, gen_mvtaclo);
	2922	+ case RX_BUILTIN_RACW2: return rx_expand_builtin_rac (exp, gen_racw);
	2923	+ case RX_BUILTIN_EMACA: return rx_expand_builtin_fromacc2
	2924	+ (target, exp, gen_emaca);
	2925	+ case RX_BUILTIN_EMSBA: return rx_expand_builtin_fromacc2
	2926	+ (target, exp, gen_emsba);
	2927	+ case RX_BUILTIN_MACLH: return rx_expand_builtin_fromacc2
	2928	+ (target, exp, gen_maclh);
	2929	+ case RX_BUILTIN_MSBHI: return rx_expand_builtin_fromacc2
	2930	+ (target, exp, gen_msbhi);
	2931	+ case RX_BUILTIN_MSBLO: return rx_expand_builtin_fromacc2
	2932	+ (target, exp, gen_msblo);
	2933	+ case RX_BUILTIN_MSBLH: return rx_expand_builtin_fromacc2
	2934	+ (target, exp, gen_msblh);
	2935	+ case RX_BUILTIN_MVFACGU: return rx_expand_builtin_fromacc2
	2936	+ (target, exp, gen_mvfacgu);
	2937	+ case RX_BUILTIN_MVFACLO: return rx_expand_builtin_fromacc2
	2938	+ (target, exp, gen_mvfaclo);
	2939	+ case RX_BUILTIN_RACL: return rx_expand_builtin_rac (exp, gen_racl);
	2940	+ case RX_BUILTIN_RDACL: return rx_expand_builtin_rac (exp, gen_rdacl);
	2941	+ case RX_BUILTIN_RDACW: return rx_expand_builtin_rac (exp, gen_rdacw);
2633	2942	default:
2634	2943	internal_error ("bad builtin code");
2635	2944	break;

--- a/gcc/config/rx/rx.h

+++ b/gcc/config/rx/rx.h

		@@ -44,6 +44,11 @@
44	44	builtin_define ("__RX600__"); \
45	45	builtin_assert ("machine=RX600"); \
46	46	} \
	47	+ else if (rx_cpu_type == RXV2) \
	48	+ { \
	49	+ builtin_define ("__RXv2__"); \
	50	+ builtin_assert ("machine=RXv2"); \
	51	+ } \
47	52	\
48	53	if (TARGET_BIG_ENDIAN_DATA) \
49	54	builtin_define ("__RX_BIG_ENDIAN__"); \

		@@ -650,6 +655,8 @@ typedef unsigned int CUMULATIVE_ARGS;
650	655	/* This macro is used to decide when RX FPU instructions can be used. */
651	656	#define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU)
652	657
	658	+#define ALLOW_RXV2_INSNS (rx_cpu_type == RXV2)
	659	+
653	660	#define BRANCH_COST(SPEED,PREDICT) 1
654	661	#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
655	662

--- a/gcc/config/rx/rx.md

+++ b/gcc/config/rx/rx.md

		@@ -35,6 +35,7 @@
35	35	(define_constants
36	36	[
37	37	(SP_REG 0)
	38	+ (R1_REG 1)
38	39	(CC_REG 16)
39	40
40	41	(UNSPEC_LOW_REG 0)

		@@ -73,8 +74,22 @@
73	74	(UNSPEC_BUILTIN_SAT 49)
74	75	(UNSPEC_BUILTIN_SETPSW 50)
75	76	(UNSPEC_BUILTIN_WAIT 51)
76		-
77		- (UNSPEC_PID_ADDR 52)
	77	+ (UNSPEC_BUILTIN_MOVCO 52)
	78	+ (UNSPEC_BUILTIN_MOVLI 53)
	79	+ (UNSPEC_BUILTIN_EMACA 54)
	80	+ (UNSPEC_BUILTIN_EMSBA 55)
	81	+ (UNSPEC_BUILTIN_MACLH 56)
	82	+ (UNSPEC_BUILTIN_MSBHI 57)
	83	+ (UNSPEC_BUILTIN_MSBLO 58)
	84	+ (UNSPEC_BUILTIN_MSBLH 59)
	85	+ (UNSPEC_BUILTIN_MVFACGU 60)
	86	+ (UNSPEC_BUILTIN_MVFACLO 61)
	87	+ (UNSPEC_BUILTIN_MVTACGU 62)
	88	+ (UNSPEC_BUILTIN_RACL 63)
	89	+ (UNSPEC_BUILTIN_RDACL 64)
	90	+ (UNSPEC_BUILTIN_RDACW 65)
	91	+
	92	+ (UNSPEC_PID_ADDR 66)
78	93	]
79	94	)
80	95

		@@ -1877,7 +1892,40 @@
1877	1892
1878	1893	;; Floating Point Instructions
1879	1894
1880		-(define_insn "addsf3"
	1895	+(define_expand "addsf3"
	1896	+ [(set (match_operand:SF 0 "register_operand" "=r")
	1897	+ (plus:SF (match_operand:SF 1 "register_operand" "r")
	1898	+ (match_operand:SF 2 "rx_source_operand" "FQr")))
	1899	+ (clobber (reg:CC CC_REG))]
	1900	+"ALLOW_RX_FPU_INSNS "
	1901	+{ if(!ALLOW_RXV2_INSNS) {
	1902	+ emit_insn(gen_addsf3_rx(operands[0],
	1903	+ operands[1],
	1904	+ operands[2]));
	1905	+ } else {
	1906	+ emit_insn(gen_addsf3_rxv2(operands[0],
	1907	+ operands[1],
	1908	+ operands[2]));
	1909	+ }
	1910	+ DONE;
	1911	+})
	1912	+
	1913	+(define_insn "addsf3_rxv2"
	1914	+ [(set (match_operand:SF 0 "register_operand" "=r,r,r,r")
	1915	+ (plus:SF (match_operand:SF 1 "register_operand" "%r,0,0,0")
	1916	+ (match_operand:SF 2 "register_operand" "r,r,F,Q")))
	1917	+ (clobber (reg:CC CC_REG))]
	1918	+ "ALLOW_RXV2_INSNS"
	1919	+ "@
	1920	+ fadd\t%2, %1, %0
	1921	+ fadd\t%2, %0
	1922	+ fadd\t%2, %0
	1923	+ fadd\t%2, %0"
	1924	+ [(set_attr "timings" "44,44,44,66")
	1925	+ (set_attr "length" "3,3,7,5")]
	1926	+)
	1927	+
	1928	+(define_insn "addsf3_rx"
1881	1929	[(set (match_operand:SF 0 "register_operand" "=r,r,r")
1882	1930	(plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1883	1931	(match_operand:SF 2 "rx_source_operand" "r,F,Q")))

		@@ -1899,7 +1947,40 @@
1899	1947	(set_attr "length" "3,7,5")]
1900	1948	)
1901	1949
1902		-(define_insn "mulsf3"
	1950	+(define_expand "mulsf3"
	1951	+ [(set (match_operand:SF 0 "register_operand" "=r,r,r")
	1952	+ (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
	1953	+ (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
	1954	+ (clobber (reg:CC CC_REG))]
	1955	+"ALLOW_RX_FPU_INSNS \|\| ALLOW_RXV2_INSNS"
	1956	+{ if(!ALLOW_RXV2_INSNS) {
	1957	+ emit_insn(gen_mulsf3_rx(operands[0],
	1958	+ operands[1],
	1959	+ operands[2]));
	1960	+ } else {
	1961	+ emit_insn(gen_mulsf3_rxv2(operands[0],
	1962	+ operands[1],
	1963	+ operands[2]));
	1964	+ }
	1965	+ DONE;
	1966	+})
	1967	+
	1968	+(define_insn "mulsf3_rxv2"
	1969	+ [(set (match_operand:SF 0 "register_operand" "=r,r,r,r")
	1970	+ (mult:SF (match_operand:SF 1 "register_operand" "%r,0,0,0")
	1971	+ (match_operand:SF 2 "rx_source_operand" "r,r,F,Q")))
	1972	+ (clobber (reg:CC CC_REG))]
	1973	+ "ALLOW_RXV2_INSNS"
	1974	+ "@
	1975	+ fmul\t%2, %1, %0
	1976	+ fmul\t%2, %0
	1977	+ fmul\t%2, %0
	1978	+ fmul\t%2, %0"
	1979	+ [(set_attr "timings" "33,33,33,55")
	1980	+ (set_attr "length" "3,3,7,5")]
	1981	+)
	1982	+
	1983	+(define_insn "mulsf3_rx"
1903	1984	[(set (match_operand:SF 0 "register_operand" "=r,r,r")
1904	1985	(mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1905	1986	(match_operand:SF 2 "rx_source_operand" "r,F,Q")))

		@@ -1910,7 +1991,40 @@
1910	1991	(set_attr "length" "3,7,5")]
1911	1992	)
1912	1993
1913		-(define_insn "subsf3"
	1994	+(define_expand "subsf3"
	1995	+ [(set (match_operand:SF 0 "register_operand" "=r")
	1996	+ (minus:SF (match_operand:SF 1 "register_operand" "r")
	1997	+ (match_operand:SF 2 "rx_source_operand" "FQr")))
	1998	+ (clobber (reg:CC CC_REG))]
	1999	+"ALLOW_RX_FPU_INSNS \|\| ALLOW_RXV2_INSNS"
	2000	+{ if(!ALLOW_RXV2_INSNS) {
	2001	+ emit_insn(gen_subsf3_rx(operands[0],
	2002	+ operands[1],
	2003	+ operands[2]));
	2004	+ } else {
	2005	+ emit_insn(gen_subsf3_rxv2(operands[0],
	2006	+ operands[1],
	2007	+ operands[2]));
	2008	+ }
	2009	+ DONE;
	2010	+})
	2011	+
	2012	+(define_insn "subsf3_rxv2"
	2013	+ [(set (match_operand:SF 0 "register_operand" "=r,r,r,r")
	2014	+ (minus:SF (match_operand:SF 1 "register_operand" "r,0,0,0")
	2015	+ (match_operand:SF 2 "rx_source_operand" "r,r,F,Q")))
	2016	+ (clobber (reg:CC CC_REG))]
	2017	+ "ALLOW_RXV2_INSNS"
	2018	+ "@
	2019	+ fsub\t%1, %2, %0
	2020	+ fsub\t%Q2, %0
	2021	+ fsub\t%Q2, %0
	2022	+ fsub\t%Q2, %0"
	2023	+ [(set_attr "timings" "44,44,44,66")
	2024	+ (set_attr "length" "3,3,7,5")]
	2025	+)
	2026	+
	2027	+(define_insn "subsf3_rx"
1914	2028	[(set (match_operand:SF 0 "register_operand" "=r,r,r")
1915	2029	(minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
1916	2030	(match_operand:SF 2 "rx_source_operand" "r,F,Q")))

		@@ -1940,6 +2054,36 @@
1940	2054	[(set_attr "timings" "22,44")
1941	2055	(set_attr "length" "3,6")]
1942	2056	)
	2057	+
	2058	+(define_insn "fixuns_truncsfsi2"
	2059	+ [(set (match_operand:SI 0 "register_operand" "=r,r")
	2060	+ (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
	2061	+ (clobber (reg:CC CC_REG))]
	2062	+ "ALLOW_RX_FPU_INSNS && ALLOW_RXV2_INSNS"
	2063	+ "ftou\t%Q1, %0"
	2064	+ [(set_attr "timings" "22,44")
	2065	+ (set_attr "length" "3,5")]
	2066	+)
	2067	+
	2068	+(define_insn "floatunssisf2"
	2069	+ [(set (match_operand:SF 0 "register_operand" "=r,r")
	2070	+ (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
	2071	+ (clobber (reg:CC CC_REG))]
	2072	+ "ALLOW_RX_FPU_INSNS && ALLOW_RXV2_INSNS"
	2073	+ "utof\t%Q1, %0"
	2074	+ [(set_attr "timings" "22,44")
	2075	+ (set_attr "length" "3,6")]
	2076	+)
	2077	+
	2078	+(define_insn "sqrtsf2"
	2079	+ [(set (match_operand:SF 0 "register_operand" "=r,r")
	2080	+ (sqrt:SF (match_operand:SF 1 "rx_source_operand" "r,Q")))
	2081	+ (clobber (reg:CC CC_REG))]
	2082	+ "ALLOW_RX_FPU_INSNS && ALLOW_RXV2_INSNS"
	2083	+ "fsqrt\t%Q1, %0"
	2084	+ [(set_attr "timings" "22,44")
	2085	+ (set_attr "length" "3,5")]
	2086	+)
1943	2087
1944	2088	;; Bit manipulation instructions.
1945	2089

		@@ -2379,87 +2523,185 @@
2379	2523	;; Multiply & Accumulate (high)
2380	2524	(define_insn "machi"
2381	2525	[(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2382		- (match_operand:SI 1 "register_operand" "r")]
	2526	+ (match_operand:SI 1 "register_operand" "r")
	2527	+ (match_operand:SI 2 "immediate_operand" "i")]
2383	2528	UNSPEC_BUILTIN_MACHI)]
2384		- ""
2385		- "machi\t%0, %1"
2386		- [(set_attr "length" "3")]
	2529	+""
	2530	+{
	2531	+ if(ALLOW_RXV2_INSNS)
	2532	+ return "machi\t%0,%1,%C2";
	2533	+ else
	2534	+ return "machi\t%0, %1";
	2535	+ }
	2536	+ [(set_attr "length" "3")]
2387	2537	)
2388	2538
2389	2539	;; Multiply & Accumulate (low)
2390	2540	(define_insn "maclo"
2391	2541	[(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2392		- (match_operand:SI 1 "register_operand" "r")]
	2542	+ (match_operand:SI 1 "register_operand" "r")
	2543	+ (match_operand:SI 2 "immediate_operand" "i")]
2393	2544	UNSPEC_BUILTIN_MACLO)]
2394	2545	""
2395		- "maclo\t%0, %1"
	2546	+{if(ALLOW_RXV2_INSNS)
	2547	+ return "machi\t%0,%1,%a2";
	2548	+else
	2549	+ return "machi\t%0, %1";
	2550	+}
2396	2551	[(set_attr "length" "3")]
2397	2552	)
2398	2553
2399	2554	;; Multiply (high)
2400	2555	(define_insn "mulhi"
2401	2556	[(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2402		- (match_operand:SI 1 "register_operand" "r")]
	2557	+ (match_operand:SI 1 "register_operand" "r")
	2558	+ (match_operand:SI 2 "immediate_operand" "i")]
2403	2559	UNSPEC_BUILTIN_MULHI)]
2404	2560	""
2405		- "mulhi\t%0, %1"
	2561	+{if(ALLOW_RXV2_INSNS)
	2562	+ return "mulhi\t%0,%1,%C2";
	2563	+else
	2564	+ return "mulhi\t%0, %1";
	2565	+}
2406	2566	[(set_attr "length" "3")]
2407	2567	)
2408	2568
2409	2569	;; Multiply (low)
2410	2570	(define_insn "mullo"
2411		- [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
2412		- (match_operand:SI 1 "register_operand" "r")]
2413		- UNSPEC_BUILTIN_MULLO)]
2414		- ""
2415		- "mullo\t%0, %1"
	2571	+ [(set (match_operand:SI 0 "register_operand" "=r")
	2572	+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
	2573	+ (match_operand:SI 2 "immediate_operand" "i")]
	2574	+ UNSPEC_BUILTIN_MULLO))]
	2575	+ ""
	2576	+{if(ALLOW_RXV2_INSNS)
	2577	+ return "mullo\t%0,%1,%a2";
	2578	+else
	2579	+ return "mullo\t%0, %1";
	2580	+}
2416	2581	[(set_attr "length" "3")]
2417	2582	)
2418	2583
2419	2584	;; Move from Accumulator (high)
2420	2585	(define_insn "mvfachi"
2421	2586	[(set (match_operand:SI 0 "register_operand" "=r")
2422		- (unspec:SI [(const_int 0)]
	2587	+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
	2588	+ (match_operand:SI 2 "immediate_operand" "i")]
2423	2589	UNSPEC_BUILTIN_MVFACHI))]
2424	2590	""
2425		- "mvfachi\t%0"
	2591	+{if(ALLOW_RXV2_INSNS)
	2592	+ return "mvfachi\t%1,%C2,%0";
	2593	+else
	2594	+ return "movfachi\t%0";
	2595	+}
2426	2596	[(set_attr "length" "3")]
2427	2597	)
2428	2598
2429		-;; Move from Accumulator (middle)
	2599	+;; Move from Accumulator (midlle)
2430	2600	(define_insn "mvfacmi"
2431	2601	[(set (match_operand:SI 0 "register_operand" "=r")
2432		- (unspec:SI [(const_int 0)]
	2602	+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
	2603	+ (match_operand:SI 2 "immediate_operand" "i")]
2433	2604	UNSPEC_BUILTIN_MVFACMI))]
2434	2605	""
2435		- "mvfacmi\t%0"
	2606	+{if(ALLOW_RXV2_INSNS)
	2607	+ return "mvfacmi\t%1,%C2,%0";
	2608	+else
	2609	+ return "movfacmi\t%0";
	2610	+}
2436	2611	[(set_attr "length" "3")]
2437	2612	)
2438	2613
2439	2614	;; Move to Accumulator (high)
2440	2615	(define_insn "mvtachi"
2441		- [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
	2616	+ [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
	2617	+ (match_operand:SI 1 "immediate_operand" "i")]
2442	2618	UNSPEC_BUILTIN_MVTACHI)]
2443	2619	""
2444		- "mvtachi\t%0"
	2620	+{if(ALLOW_RXV2_INSNS)
	2621	+ return "mvtachi\t%0,%C1";
	2622	+else
	2623	+ return "mvtachi\t%0";
	2624	+}
2445	2625	[(set_attr "length" "3")]
2446	2626	)
2447	2627
2448	2628	;; Move to Accumulator (low)
2449	2629	(define_insn "mvtaclo"
2450		- [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
	2630	+ [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
	2631	+ (match_operand:SI 1 "immediate_operand" "i")]
2451	2632	UNSPEC_BUILTIN_MVTACLO)]
2452	2633	""
2453		- "mvtaclo\t%0"
	2634	+{if(ALLOW_RXV2_INSNS)
	2635	+ return "mvtaclo\t%0,%C1";
	2636	+else
	2637	+ return "mvtaclo\t%0";
	2638	+}
	2639	+ [(set_attr "length" "3")]
	2640	+)
	2641	+
	2642	+;; Move from Accumulator (gurd)
	2643	+(define_insn "mvfacgu"
	2644	+ [(set (match_operand:SI 0 "register_operand" "=r")
	2645	+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
	2646	+ (match_operand:SI 2 "immediate_operand" "i")]
	2647	+ UNSPEC_BUILTIN_MVFACGU))]
	2648	+ "ALLOW_RXV2_INSNS"
	2649	+ "mvfacgu\t%1,%C2,%0"
	2650	+ [(set_attr "length" "3")]
	2651	+)
	2652	+
	2653	+;; Move from Accumulator (low)
	2654	+(define_insn "mvfaclo"
	2655	+ [(set (match_operand:SI 0 "register_operand" "=r")
	2656	+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
	2657	+ (match_operand:SI 2 "immediate_operand" "i")]
	2658	+ UNSPEC_BUILTIN_MVFACLO))]
	2659	+ "ALLOW_RXV2_INSNS"
	2660	+ "mvfaclo\t%1,%C2,%0"
2454	2661	[(set_attr "length" "3")]
2455	2662	)
2456	2663
2457	2664	;; Round Accumulator
2458	2665	(define_insn "racw"
2459		- [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
	2666	+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
	2667	+ (match_operand:SI 1 "immediate_operand" "i")]
2460	2668	UNSPEC_BUILTIN_RACW)]
2461	2669	""
2462		- "racw\t%0"
	2670	+{if(ALLOW_RXV2_INSNS)
	2671	+ return "racw\t%0,%C1";
	2672	+else
	2673	+ return "racw\t%0";
	2674	+}
	2675	+ [(set_attr "length" "3")]
	2676	+)
	2677	+
	2678	+;; Round Accumulator
	2679	+(define_insn "racl"
	2680	+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
	2681	+ (match_operand:SI 1 "immediate_operand" "i")]
	2682	+ UNSPEC_BUILTIN_RACL)]
	2683	+ "ALLOW_RXV2_INSNS"
	2684	+ "racl\t%0,%C1"
	2685	+ [(set_attr "length" "3")]
	2686	+)
	2687	+
	2688	+;; Round Accumulator
	2689	+(define_insn "rdacl"
	2690	+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
	2691	+ (match_operand:SI 1 "immediate_operand" "i")]
	2692	+ UNSPEC_BUILTIN_RDACL)]
	2693	+ "ALLOW_RXV2_INSNS"
	2694	+ "rdacl\t%0,%C1"
	2695	+ [(set_attr "length" "3")]
	2696	+)
	2697	+
	2698	+;; Round Accumulator
	2699	+(define_insn "rdacw"
	2700	+ [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
	2701	+ (match_operand:SI 1 "immediate_operand" "i")]
	2702	+ UNSPEC_BUILTIN_RDACW)]
	2703	+ "ALLOW_RXV2_INSNS"
	2704	+ "rdacw\t%0,%C1"
2463	2705	[(set_attr "length" "3")]
2464	2706	)
2465	2707

		@@ -2477,6 +2719,67 @@
2477	2719	(set_attr "timings" "1010")]
2478	2720	)
2479	2721
	2722	+;; Multiply & Accumulate (low)
	2723	+(define_insn "emaca"
	2724	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2725	+ (match_operand:SI 1 "register_operand" "r")
	2726	+ (match_operand:SI 2 "immediate_operand" "i")]
	2727	+ UNSPEC_BUILTIN_EMACA)]
	2728	+ "ALLOW_RXV2_INSNS"
	2729	+ "emacs\t%0,%1,%a2";
	2730	+ [(set_attr "length" "3")]
	2731	+)
	2732	+
	2733	+(define_insn "emsba"
	2734	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2735	+ (match_operand:SI 1 "register_operand" "r")
	2736	+ (match_operand:SI 2 "immediate_operand" "i")]
	2737	+ UNSPEC_BUILTIN_EMSBA)]
	2738	+ "ALLOW_RXV2_INSNS"
	2739	+ "emsbs\t%0,%1,%a2";
	2740	+ [(set_attr "length" "3")]
	2741	+)
	2742	+
	2743	+(define_insn "maclh"
	2744	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2745	+ (match_operand:SI 1 "register_operand" "r")
	2746	+ (match_operand:SI 2 "immediate_operand" "i")]
	2747	+ UNSPEC_BUILTIN_MACLH)]
	2748	+ "ALLOW_RXV2_INSNS"
	2749	+ "maclh\t%0,%1,%a2";
	2750	+ [(set_attr "length" "3")]
	2751	+)
	2752	+
	2753	+(define_insn "msbhi"
	2754	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2755	+ (match_operand:SI 1 "register_operand" "r")
	2756	+ (match_operand:SI 2 "immediate_operand" "i")]
	2757	+ UNSPEC_BUILTIN_MSBHI)]
	2758	+ "ALLOW_RXV2_INSNS"
	2759	+ "msbhi\t%0,%1,%a2";
	2760	+ [(set_attr "length" "3")]
	2761	+)
	2762	+
	2763	+(define_insn "msblo"
	2764	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2765	+ (match_operand:SI 1 "register_operand" "r")
	2766	+ (match_operand:SI 2 "immediate_operand" "i")]
	2767	+ UNSPEC_BUILTIN_MSBLO)]
	2768	+ "ALLOW_RXV2_INSNS"
	2769	+ "msblo\t%0,%1,%a2";
	2770	+ [(set_attr "length" "3")]
	2771	+)
	2772	+
	2773	+(define_insn "msblh"
	2774	+ [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
	2775	+ (match_operand:SI 1 "register_operand" "r")
	2776	+ (match_operand:SI 2 "immediate_operand" "i")]
	2777	+ UNSPEC_BUILTIN_MSBLH)]
	2778	+ "ALLOW_RXV2_INSNS"
	2779	+ "msblh\t%0,%1,%a2";
	2780	+ [(set_attr "length" "3")]
	2781	+)
	2782	+
2480	2783	;;---------- Arithmetic ------------------------
2481	2784
2482	2785	;; Byte swap (two 16-bit values).

		@@ -2639,3 +2942,5 @@
2639	2942	[(set_attr "length" "16")
2640	2943	(set_attr "timings" "22")]
2641	2944	)
	2945	+
	2946	+(include "sync.md")

--- a/gcc/config/rx/rx.opt

+++ b/gcc/config/rx/rx.opt

		@@ -64,6 +64,9 @@ Enum(rx_cpu_types) String(rx600) Value(RX600)
64	64	EnumValue
65	65	Enum(rx_cpu_types) String(rx100) Value(RX100)
66	66
	67	+EnumValue
	68	+Enum(rx_cpu_types) String(rxv2) Value(RXV2)
	69	+
67	70	;---------------------------------------------------
68	71
69	72	mbig-endian-data

--- /dev/null

+++ b/gcc/config/rx/sync.md

		@@ -0,0 +1,191 @@
	1	+;; GCC machine description for RXv2 synchronization instructions.
	2	+;; Copyright (C) 2011-2015 Free Software Foundation, Inc.
	3	+;;
	4	+;; This file is part of GCC.
	5	+;;
	6	+;; GCC is free software; you can redistribute it and/or modify
	7	+;; it under the terms of the GNU General Public License as published by
	8	+;; the Free Software Foundation; either version 3, or (at your option)
	9	+;; any later version.
	10	+;;
	11	+;; GCC is distributed in the hope that it will be useful,
	12	+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+;; GNU General Public License for more details.
	15	+;;
	16	+;; You should have received a copy of the GNU General Public License
	17	+;; along with GCC; see the file COPYING3. If not see
	18	+;; <http://www.gnu.org/licenses/>.
	19	+;;
	20	+;;
	21	+
	22	+(define_c_enum "unspec" [
	23	+ UNSPEC_ATOMIC
	24	+])
	25	+
	26	+(define_c_enum "unspecv" [
	27	+ UNSPECV_CMPXCHG_1
	28	+ UNSPECV_CMPXCHG_2
	29	+ UNSPECV_CMPXCHG_3
	30	+])
	31	+
	32	+(define_code_iterator FETCHOP [plus minus ior xor and])
	33	+(define_code_attr fetchop_name
	34	+ [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
	35	+
	36	+(define_code_attr fetchop_constraint_1_llcs
	37	+ [(plus "ri") (minus "r") (ior "ri") (xor "ri") (and "ri")])
	38	+
	39	+;;------------------------------------------------------------------------------
	40	+;; comapre and swap
	41	+
	42	+(define_expand "atomic_compare_and_swapsi"
	43	+ [(match_operand:SI 0 "register_operand") ;; bool success output
	44	+ (match_operand:SI 1 "register_operand") ;; oldval output
	45	+ (match_operand:SI 2 "memory_operand") ;; memory
	46	+ (match_operand:SI 3 "general_operand") ;; expected input
	47	+ (match_operand:SI 4 "general_operand") ;; newval input
	48	+ (match_operand:SI 5 "const_int_operand") ;; is_weak
	49	+ (match_operand:SI 6 "const_int_operand") ;; success model
	50	+ (match_operand:SI 7 "const_int_operand")] ;; failure model
	51	+ ""
	52	+{
	53	+ rtx mem = operands[2];
	54	+ rtx old_val = gen_lowpart (SImode, operands[1]);
	55	+ rtx exp_val = operands[3];
	56	+ rtx new_val = operands[4];
	57	+
	58	+ if (ALLOW_RXV2_INSNS) {
	59	+ emit_insn (gen_atomic_compare_and_swapsi_1 (old_val, mem,
	60	+ exp_val, new_val));
	61	+
	62	+ DONE;
	63	+ } else {
	64	+ FAIL;
	65	+ }
	66	+})
	67	+
	68	+(define_insn "atomic_compare_and_swapsi_1"
	69	+ [(set (match_operand:SI 0 "register_operand" "=&r")
	70	+ (unspec_volatile:SI
	71	+ [(match_operand:SI 1 "memory_operand" "=q")
	72	+ (match_operand:SI 2 "general_operand" "ri")
	73	+ (match_operand:SI 3 "general_operand" "ri")]
	74	+ UNSPECV_CMPXCHG_1))
	75	+ (set (match_dup 1)
	76	+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_2))
	77	+ (set (reg:SI CC_REG)
	78	+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))
	79	+ (clobber (reg:SI CC_REG))
	80	+ (clobber (reg:SI R1_REG))]
	81	+ "ALLOW_RXV2_INSNS"
	82	+ "\r0: movli %1,r1
	83	+ cmp %2,r1
	84	+ bne 0f
	85	+ mov r1,%0
	86	+ mov %3,r1
	87	+ movco r1,%1
	88	+ tst r1,r1
	89	+ bne 0b
	90	+0:"
	91	+ [(set_attr "length" "19")])
	92	+
	93	+;;------------------------------------------------------------------------------
	94	+;; read - write - return old value
	95	+(define_insn "atomic_exchangesi"
	96	+ [(set (match_operand:SI 0 "register_operand" "=&r") ;; oldval output
	97	+ (match_operand:SI 1 "memory_operand" "=m")) ;; memory
	98	+ (match_operand:SI 3 "const_int_operand") ;; memory model
	99	+ (set (match_dup 1)
	100	+ (match_operand:SI 2 "register_operand" "0"))] ;; input
	101	+ ""
	102	+ "xchg %1,%0"
	103	+ [(set_attr "length" "4")])
	104	+
	105	+;;------------------------------------------------------------------------------
	106	+;; read - add\|sub\|or\|and\|xor\|nand - write - return old value
	107	+
	108	+(define_insn "atomic_fetch_<fetchop_name>si"
	109	+ [(set (match_operand:SI 0 "register_operand" "=&mr")
	110	+ (match_operand:SI 1 "memory_operand" "=mr"))
	111	+ (set (match_dup 1)
	112	+ (unspec:SI
	113	+ [(FETCHOP:SI (match_dup 1)
	114	+ (match_operand:SI 2 "general_operand" "g"))]
	115	+ UNSPEC_ATOMIC))
	116	+ (match_operand:SI 3 "const_int_operand")
	117	+ (clobber (reg:SI CC_REG))
	118	+ (clobber (reg:SI R1_REG))]
	119	+ "ALLOW_RXV2_INSNS"
	120	+ "\r0: movli %1,r1
	121	+ mov r1,%0
	122	+ <fetchop_name> %2,r1
	123	+ movco r1,%1
	124	+ tst r1,r1
	125	+ beq 0b";
	126	+ [(set_attr "length" "15")])
	127	+
	128	+(define_insn "atomic_fetch_nandsi"
	129	+ [(set (match_operand:SI 0 "register_operand" "=&r")
	130	+ (match_operand:SI 1 "memory_operand" "=q"))
	131	+ (set (match_dup 1)
	132	+ (unspec:SI
	133	+ [(not:SI (and:SI (match_dup 1)
	134	+ (match_operand:SI 2 "general_operand" "ri")))]
	135	+ UNSPEC_ATOMIC))
	136	+ (match_operand:SI 3 "const_int_operand")
	137	+ (clobber (reg:SI CC_REG))
	138	+ (clobber (reg:SI R1_REG))]
	139	+ "ALLOW_RXV2_INSNS"
	140	+ "\r0: movli %1,r1
	141	+ mov r1,%0
	142	+ and %2,r1
	143	+ not r1
	144	+ movco r1,%1
	145	+ tst r1,r1
	146	+ beq 0b"
	147	+ [(set_attr "length" "16")])
	148	+
	149	+;;------------------------------------------------------------------------------
	150	+;; read - add\|sub\|or\|and\|xor\|nand - write - return new value
	151	+
	152	+(define_insn "atomic_<fetchop_name>_fetchsi"
	153	+ [(set (match_operand:SI 0 "register_operand" "=&r")
	154	+ (FETCHOP:SI
	155	+ (match_operand:SI 1 "memory_operand" "=m")
	156	+ (match_operand:SI 2 "general_operand" "ri")))
	157	+ (set (match_dup 1)
	158	+ (unspec:SI
	159	+ [(FETCHOP:SI (match_dup 1) (match_dup 2))]
	160	+ UNSPEC_ATOMIC))
	161	+ (match_operand:SI 3 "const_int_operand" "")
	162	+ (clobber (reg:SI CC_REG))]
	163	+ "ALLOW_RXV2_INSNS"
	164	+ "\r0: movli %1,%0
	165	+ <fetchop_name> %2,%0
	166	+ movco %0,%1
	167	+ tst %0,%0
	168	+ beq 0b
	169	+ mov.L %1,%0"
	170	+ [(set_attr "length" "15")])
	171	+
	172	+(define_insn "atomic_nand_fetchsi"
	173	+ [(set (match_operand:SI 0 "register_operand" "=&r")
	174	+ (not:SI (and:SI
	175	+ (match_operand:SI 1 "memory_operand" "=q")
	176	+ (match_operand:SI 2 "general_operand" "ri"))))
	177	+ (set (match_dup 1)
	178	+ (unspec:SI
	179	+ [(not:SI (and:SI (match_dup 1) (match_dup 2)))]
	180	+ UNSPEC_ATOMIC))
	181	+ (match_operand:SI 3 "const_int_operand")
	182	+ (clobber (reg:SI CC_REG))]
	183	+ "ALLOW_RXV2_INSNS"
	184	+ "\r0: movli %1,%0
	185	+ and %2,%0
	186	+ not %0
	187	+ movco %0,%1
	188	+ tst %0,%0
	189	+ bf 0b
	190	+ mov.L %1,%0"
	191	+ [(set_attr "length" "16")])

--- a/gcc/config/rx/t-rx

+++ b/gcc/config/rx/t-rx

		@@ -30,6 +30,8 @@ MULTILIB_DIRNAMES = 64-bit-double no-fpu-libs big-endian-data pid
30	30
31	31	MULTILIB_OPTIONS += mno-allow-string-insns
32	32	MULTILIB_DIRNAMES += no-strings
	33	+MULTILIB_OPTIONS += mcpu=rxv2
	34	+MULTILIB_DIRNAMES += v2
33	35
34	36	MULTILIB_MATCHES = nofpu=mnofpu nofpu=mcpu?rx200 nofpu=mcpu?rx100
35	37

--- a/gcc/doc/md.texi

+++ b/gcc/doc/md.texi

		@@ -3445,6 +3445,8 @@ A constant in the range @minus{}8388608 to 8388607, inclusive.
3445	3445	@item Uint04
3446	3446	A constant in the range 0 to 15, inclusive.
3447	3447
	3448	+@item q
	3449	+A register indirect adressing.
3448	3450	@end table
3449	3451
3450	3452	@item S/390 and zSeries---@file{config/s390/s390.h}

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